An embodiment relates to the erase method of a flash device and, more particularly, to the erase method of a flash device, which is capable of simplifying the erase operation and also improving the distributions of a threshold voltage of an erase state.
The operations of a semiconductor device may include a program operation, an erase operation, and a read operation. During the program operation and the erase operation, a verification operation is performed. From among them, the erase operation is described by taking a flash device as an example.
The erase operation of the flash device may be performed on a memory-cell-block basis.
In more detail, the erase operation may be performed by supplying the bit line of a selected memory cell block with an erase voltage (for example, 20V) and all word lines of the selected memory cell block with a ground voltage (for example, 0V). At this time, a selected bit line is supplied with the erase voltage, and unselected bit lines are floated or applied with a ground voltage (for example, 0V). In a flash device, the distance between bit lines is generally narrower than the distance between other wirings (for example, gate lines). Accordingly, as the potential difference between neighbor bit lines increases, an interference effect is likely to occur. For example, since the potential difference between a selected bit line and an unselected bit line is large (for example, about 20 V), capacitive coupling may occur between the bit lines, where the voltage of the unselected bit line may rise due to the capacitive coupling. To prevent this problem, operations for preventing such an unintended voltage rise are desired. However, such operations often make complicated the erase operation and may also increase the time for performing the erase operation.